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1 ? fn8159.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copy right intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x9111 single supply/low powe r/1024-tap/spi bus single digitally-controlled (xdcp?) potentiometer the x9111 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 1023 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? 1024 resistor taps ? 10-bit resolution ? spi serial interface for write, read, and transfer operations of the potentiometer ? wiper resistance, 40 ? typical @ 5v ? four non-volatile data registers ? non-volatile storage of multiple wiper positions ? power on recall. loads saved wiper position on power up. ? standby current < 3a max ?v cc : 2.7v to 5.5v operation ?100k ? end to end resistance ? 100 yr. data retention ? endurance: 100, 000 data changes per bit per register ? 14-lead tssop, 15-lead csp (chip scale packaging) ? low power cmos ? single supply version of the x9110 functional diagram r h r l bus r w interface & control pot v cc v ss spi bus address data status write read wiper 1024-taps transfer nc 100k ? power on recall wiper counter register (wcr) data registers (dr0-dr3) control interface data sheet february 28, 2005
2 fn8159.0 february 28, 2005 detailed functional diagram circuit level applications ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage amplifier circuit ? set the output voltag e of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level applications ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home enterta inment systems ? provide the variable dc bias for tuners in rf wireless systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems cs sck a0 so si hold wp interface and control circuitry v cc v ss dr0 dr1 dr2 dr3 wiper counter register (wcr) r h r l data r w 1024-taps 100k ? control power on recall a1
3 fn8159.0 february 28, 2005 pin configuration pin descriptions bus interface pins serial output (so) so is a serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9111. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 , a 1 ) the address inputs are used to set the 8-bit slave address. a match in the slave address serial data stream must be made with the address input (a1?a0) in order to initiate communication with the x9111. v cc r l v ss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 nc r w cs a1 tssop r h csp a0 so si hold sck x9111 wp x9111 a b c d e r l v cc so r h nc a0 r w nc cs hold wp sck a1 v ss si 321 pin descriptions pin (tssop) pin (csp) symbol function 1a3 soserial data output 2 b3 a0 device address 3 b2, c2 nc no connect 4c3 cs chip select 5 d3 sck serial clock 6 e3 si serial data input 7e2 v ss system ground 8d2 wp hardware write protect 9 e1 a1 device address 10 d1 hold device select. pause the serial bus 11 c1 r w wiper terminal of the potentiometer 12 b1 r h high terminal of the potentiometer 13 a1 r l low terminal of the potentiometer 14 a2 v cc system supply voltage
4 fn8159.0 february 28, 2005 chip select (cs ) when cs is high, the x9111 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9111, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w the wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. bias supply pins system supply voltage (v cc ) and supply ground (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins no connect (nc) pin should be left open. this pin is used for intersil manufacturing and test purposes. principles of operation device description serial interface the x9111 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked-in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be co nnected together, since they have three state outputs. this can help to re duce system pin count. array description the x9111 is comprised of a resistor array (see figure 1). the array contains the equivalent of 1023 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within the individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the 10-bits of the wcr (wcr[9:0]) are decoded to select, and enable, one of 1024 switches. serial data path from interface register 0 serial bus input parallel bus input counter register r h r l r w 10 10 c o u n t e r d e c o d e if wcr = 000[hex] then r w = r l if wcr = 3ff[hex] then r w = r h wiper (wcr) (dr0) circuitry register 1 (dr1) register 2 (dr2) register 3 (dr3) figure 1. detailed potentiometer block diagram
5 fn8159.0 february 28, 2005 wiper counter register (wcr) the x9111 contains a wiper co unter register (see table 1) for the xdcp potentiometer. the wcr is equivalent to a serial-in, parallel-out regi ster/counter with its outputs decoded to select one of 1024 switches along its resistor array. the contents of the wcr can be altered in one of three ways: (1) it may be written directly by the host via the write wiper counter register inst ruction (serial load); (2) it may be written indirectly by tr ansferring the contents of one of four associated data registers via the xfr data register; (3) it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9111 is powered-down. although the register is automatically loaded with the value in r0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the r0 value into the wcr. data registers (dr3 to dr0) the potentiometer has four 10-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wiper counter register. all operations changing data in one of the da ta registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not re quire storage of multiple settings for the potentiometer, the data registers can be used as regular memory locati ons for system parameters or user preference data. a dr[9:0] is used to store one of the 1024 wiper position (0 ~1023). table 2 status register (sr) this 1-bit status register is used to store the system status (see table 3). wip: write in progress st atus bit, read only. ? when wip=1, indicates that high-voltage write cycle is in progress. ? when wip=0, indicates that no high-voltage write cycle is in progress. device instructions identification byte (id and a) the first byte sent to the x9111 from the host, following a cs going high to low, is call ed the identification byte. the most significant four bits of the slave address are a device type identifier. the id[3:0] bits is the device id for the x9111; this is fixed as 0101[b] (refer to table 4). the a1?a0 bits in the id byte are the internal slave address. the physical device address is defined by the state of the a1?a0 input pins. the slave address is externally specified by the user. the x9111 compares the serial data stream with the address input state; a successful compare of the address bits is required for the x9111 to successfully continue the command sequence. only the device whose slave address matches the incoming device ad dress sent by the master executes the instruction. the a1?a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the r/w bit is used to set the device to either read or write mode. instruction byte and register selection the next byte sent to the x911 1 contains the instruction and register pointer information. the three most significant bits are used provide the instruction opcode (i[2:0]). the rb and ra bits point to one of the four registers. the format is shown in table 5. table 3. status register, sr (1-bit) table 1. wiper latch, wl (10-bit), wcr9?wcr0: used to store the current wiper position (volatile, v) wcr9 wcr8 wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvvvv (msb) (lsb) table 2. data register, dr (10-bit), bit 9?bit 0: used to store wiper positions or data (non-volatile, nv) bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nv nv nv nv nv nv nv nv nv nv msb lsb wip (lsb)
6 fn8159.0 february 28, 2005 it five of the seven instructions are four bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the selected pot, ? write wiper counter register ? change current wiper position of the selected pot, ? read data register ? read the contents of the selected data register; ? write data register ? write a new value to the selected data register. ? read status ? this command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the basic sequence of the four by te instructions is illustrated in figure 3. these four-byte instructions exchange data between the wcr and one of t he data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by twrl. a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of twr to complete. the transfer can occur between the potentiometer and one of its associated registers. the read status regi ster instruction is the only unique format (see figure 4). two instructions require a two-byte sequence to complete (see figure 2). these instructi ons transfer dat a between the host and the x9111; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ?this transfers the contents of one specified data register to the associated wiper counter register. ? xfr wiper counter register to data register ? this transfers the contents of the specified wiper counter register to the specified associated data register. see instruction format for more details. write in process (wip bit) the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal writ e operation can be monitored by a write in process bit (wip). th e wip bit is read with a read status command (see figure 4). power up and down requirements there are no restrictions on the power-up condition of v cc and the voltages applied to the potentiometer pins provided that the v cc is always more positive than or equal to the voltages at r h , r l , and r w , i.e., v cc r h , r l , r w . there are no restrictions on the power-down condition. however, the datasheet parameters for the dcp do not apply until 1millisecond after v cc reaches its final value. table 3. identification byte format id3 id2 id1 id0 0 a1 a0 r/w 0101 (msb) (lsb) device type internal slave identifier address read or write bit table 4. instruction byte format i2 i1 i0 0 rb ra 0 0 (msb) (lsb) instruction opcode register selection rb ra register 0 0 1 1 0 1 0 1 dr0 dr1 dr2 dr3
7 fn8159.0 february 28, 2005 id3 id2 id1 id0 0 a1 a0 i2 i1 i0 rb ra sck si cs 0101 r/w device id internal instruction opcode address register 0 0 0 0 address 0 0 figure 2. two-byte instruction sequence id3 id2 id1 id0 0 a0 r/w i2 00 sck si 0 0 x x0 0 xx x w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs i1 i0 0 rb ra 0 101 0 xx x device id internal address instruction opcode register address wiper position a1 figure 3. four-byte instruction sequence (wri te or read for wcr or data registers) id3 id2 id1 id0 0 a0 r/w i2 00 sck si 1 0 x x0 0 xxx wip cs i1 i0 0 rb ra 0101 0 xx x device id internal address instruction opcode register address status bit x x 0 00 0 0 0 0 a1 figure 4. four-byte instruction sequence (read status registers)
8 fn8159.0 february 28, 2005 instruction format table 5. instruction set instruction instruction set operation r/w i 3 i 2 i 1 0rbra0 0 read wiper counter register 1 1 0 0 0 0 0 0 0 read the contents of the wiper counter register write wiper counter register 0 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 1 0 1 0 1/0 1/0 0 0 read the contents of the data register pointed to rb-ra write data register 0 1 1 0 0 1/0 1/0 0 0 write new value to the data register pointed to rb-ra xfr data register to wiper counter register 1 1 1 0 0 1/0 1/0 0 0 transfer the contents of the data register pointed to by rb-ra to the wiper counter register xfr wiper counter register to data register 0 1 1 1 0 1/0 1/0 0 0 transfer the contents of the wiper counter register to the data register pointed to by rb-ra read status (wip bit) 1 0 1 0 0 0 0 0 1 read the status of the internal write cycle, by checking the wip bit (read status register). note: 1/0 = data is one or zero read wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode register addresses wiper position (sent by x9111 on so) wiper position (sent by x9111 on so) cs rising edge 01010a1a0 r/ w = 1 10000000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 write wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode register addresses wiper position (sent by master on si) wiper position (sent by master on si) cs rising edge 01010a1a0 r/ w = 0 10100000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 read data register (dr) cs falling edge device type identifier device addresses instruction opcode register addresses wiper position (sent by x9111 on so) wiper position (sent by x9111 on so) cs rising edge 01010a1a0 r/ w = 1 1010rbra00xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 write data register (dr) cs falling edge device type identifier device addresses instruction opcode register addresses wiper position or data (sent by master on si) wiper position or data (sent by master on si) cs rising edge high-voltage write cycle 01010a1a0 r/ w = 0 1100 r b r a 0 0xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0
9 fn8159.0 february 28, 2005 transfer data register (dr) to wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode register addresses cs rising edge 01010a1a0 r/ w = 1 1100rbra00 transfer wiper counter register (wcr) to data register (dr) cs falling edge device type identifier device addresses instruction opcode register addresses cs rising edge high-voltage write cycle 01010a1a0 r/ w = 0 1110 rb ra 0 0 read status register (sr) cs falling edge device type identifier device addresses instruction opcode register addresses status data (sent by slave on so) status data (sent by slave on so) cs rising edge 01010a1a0 r/ w = 1 01000001 xxxxxxxx0 0 00000 wi p notes: 1. ?a0 and a1?: stand for the device address sent by the master. 2. wcrx refers to wiper position data in the wiper counter register 3. ?x?: don?t care.
10 fn8159.0 february 28, 2005 absolute maximum ratings recommended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on sck any address input with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v ? v = | (vh?vl) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300 c i w (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (v cc ) limits x9111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 10% x9111-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. analog characteristics over recommended industrial operation conditions unless otherwise stated. symbol parameter test conditions min typ max units r total end to end resistance 100 k ? end to end resistance tolerance 20 % power rating 25c, each pot 50 mw i w wiper current 3 ma r w wiper resistance wiper current = 50a, v cc = 5v 40 110 ? wiper current = 50a, v cc = 3v 150 300 ? v term voltage on any r h or r l pin v ss = 0v v ss 5v noise ref: 1v -120 dbv resolution 1.6 % absolute linearity (note 1) r w(n)(actual) -r w(n)(expected) , where n = 8 to 1006 1 mi (note 3) r w(n)(actual) -r w(n)(expected) (note 6) 1.5 2.0 mi (note 3) relative linearity (note 2) r w(m + 1) -[r w(m) + mi], where m = 8 to 1006 0.5 mi (note 3) r w(m + 1) -[r w(m) + mi] (note 6) 0.5 1.0 mi (note 3) temperature coefficient of r total 300 ppm/c ratiometric temp. coefficient 20 ppm/c c h /c l /c w potentiometer capacitancies see macro model 10/10/25 pf notes: 1. absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 2. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 3. mi = rtot/1023 or (r h ? r l )/1023, single pot 4. n = 0, 1, 2, ?,1023; m =0, 1, 2, ?, 1022. 5. esd rating on rh, rl, rw pins is 1.5kv (hbm, 1.0a leakage maximum), esd rating on all other pins is 2.0kv.
11 fn8159.0 february 28, 2005 d.c. operating characteristics over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min. typ. max. units i cc1 v cc supply current (active) f sck = 2.5 mhz, so = open, v cc = 5.5v other inputs = v ss 400 a i cc2 v cc supply current (nonvolatile write) f sck = 2.5mhz, so = open, v cc = 5.5v other inputs = v ss 15ma i sb v cc current (standby) sck = si = v ss , addr. = v ss , cs = v cc = 5.5v 3 a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc 10 a v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol output low voltage i ol = 3ma 0.4 v v ol output low voltage i oh = -1ma, v cc +3v v cc - 0.8 v v ol output low voltage i oh = -0.4ma, v cc +3v v cc - 0.4 v endurance and data retention parameter min units minimum endurance 100,000 data changes per bit per register data retention 100 years capacitance symbol test test conditions max units c in/out (note 6) input/output capacitance (si) v out = 0v 8 pf c out (note 6) output capacitance (so) v out = 0v 8 pf c in (note 6) input capacitance (a0, cs , wp , hold , and sck) v in = 0v 6 pf power-up timing symbol parameter min max units t r v cc (note 6) v cc power-up rate 0.2 50 v/ms t pur (note 7) power-up to initiation of read operation 1 ms t puw (note 7) power-up to initiation of write operation 50 ms notes: 6. this parameter is not 100% tested. 7. t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the specific instruction can be issued. these parameters are not 100% tested. a.c. test conditions i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5
12 fn8159.0 february 28, 2005 equivalent a.c. load circuit 5v 1462 ? 100pf so pin r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 2714 ? 3v 1382 ? 100pf so pin 1217 ? ac timing symbol parameter min max units f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 400 ns t wh ssi/spi clock high time 150 ns t wl ssi/spi clock low time 150 ns t lead lead time 150 ns t lag lag time 150 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 50 ns t fi si, sck, hold and cs input fall time 50 ns t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 50 ns t hh hold hold time 50 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 100 ns t wpasu wp , a0, a1 setup time 0 ns t wpah wp , a0, a1 hold time 0 ns
13 fn8159.0 february 28, 2005 symbol table high-voltage write cycle timing symbol parameter typ max units t wr high-voltage write cycle time (store instructions) 5 10 ms xdcp timing symbol parameter min max units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 5 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance
14 fn8159.0 february 28, 2005 timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo
15 fn8159.0 february 28, 2005 xdcp timing (for all load instructions) write protect and device address pins timing applications information basic configurations of electronic potentiometers ... cs sck si msb lsb r w t wrl ... so high impedance cs wp a0 a1 t wpasu t wpah (any instruction) v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current
16 fn8159.0 february 28, 2005 application circuits noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + ? v s v o r 2 r 1 } }
17 fn8159.0 february 28, 2005 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o
18 fn8159.0 february 28, 2005 packaging information *true no-connect bump 9111tbz yww i lot# 15-bump chip scale package (csp b15) package outline drawing a f k mj l b d e c e top view (sample marking) bottom view (bumped side) side view side view a3 a2 a1 b3 b2 b1 c3 c2 c1 d3 d2 d1 e3 e2 e1 package dimensions symbol millimeters min nominal max package width a 2.535 2.565 2.595 package length b 3.272 3.302 3.332 package height c 0.644 0.677 0.710 body thickness d 0.444 0.457 0.470 ball height e 0.220 0.240 0.260 ball diameter f 0.310 0.330 0.350 ball pitch - width j 0.5 ball pitch - length k 0.5 ball to edge spacing -width l 0.758 0.783 0.808 ball to edge spacing - length m 0.626 0.651 0.676 ball matrix 321 asovccr l b a0 nc* r h c cs nc* r w d sck wp hold esivssa1
19 fn8159.0 february 28, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package code v14 see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8159.0 february 28, 2005 ordering information device x9111 p t v y v cc limits blank = 5v 10% ?2.7 = 2.7 to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = -40 c to +85 c package v14 = 14-lead tssop b15 = 15-lead csp potentiometer organization pot t = 100k ?

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